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2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP Preliminary Technical Data AD5541A/AD5542A/AD5512A
FEATURES
Low power, 1 LSB INL nanoDACs AD5541A: 16 bits AD5542A: 16 bits AD5512A: 12 bits 2.7 V to 5.5 V single-supply operation Low glitch: 0.5 nV-s Unbuffered voltage output capable of driving 60 k loads directly VLOGIC pin provides 1.8 V digital interface capability Hardware CLR and LDAC functions 50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface standards Power-on reset clears DAC output to zeroscale and midscale Schmitt trigger inputs Available in 3 mm x 3 mm 16-LFCSP, 10-LFCSP, and 8-LFCSP Also available in10-MSOP and 16-TSSOP
range of -40C to 105C.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. AD5541A
APPLICATIONS
Automatic test equipment Precision Source-measure Instruments Data Acquisition Systems Medical Instrumentation Aerospace Instrumentation Communications Infrastructure equipment Industrial Control
Figure 2. AD5541A-1
GENERAL DESCRIPTION
The AD5541A/AD5542A/AD5512A1 are single, 16-/16-/12-bit, serial input, unbuffered voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The AD5541A/AD5542A/AD5512A utilize a versatile 3-wire interface that is compatible with a 50 MHz SPI, QSPITM, MICROWIRETM, and DSP interface standards. These DACs provide 16-/12-bit performance without any adjustments. The DAC output is unbuffered, which reduces power consumption and offset errors contributed to by an output buffer. The AD5542A/AD5512A can be operated in bipolar mode, which generates a VREF output swing. The AD5542A/AD5512A also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD5541A is available in 10-lead 3 mm x 3 mm LFCSP and 10-lead MSSOP. The AD5541A-1 is available in 8-lead 3 mm x 3 mm LFCSP. The AD5542A/AD5512A are available in 16-lead 3 mm x 3 mm LFCSP and the AD5542A is also available in 16-lead TSSOP. The AD5542A-1 is available in 10-lead LFCSP. The AD5541A and AD5542A are specified over a temperature
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 3. AD5542A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
AD5541A/AD5542A/AD5512A
Preliminary Technical Data
Figure 4.
1
All references to the AD5541A/AD5542A/AD5512A incorporate all models (see Ordering Guide) including the AD5541A-1/AD5542A-1 unless specified.
Rev. PrA| Page 2 of 24
Preliminary Technical Data TABLE OF CONTENTS
Features ............................................................................................... 1 Applications ....................................................................................... 1 General Description .......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ................................................................................ 3 Specifications ..................................................................................... 4 Timing Characteristics ................................................................. 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ............................ 7 Typical Performance Characteristics .............................................. 9 Terminology .....................................................................................12 Theory of Operation .......................................................................13 Digital-to-Analog Section ..........................................................13 Serial Interface .............................................................................13 Unipolar Output Operation .......................................................13
AD5541A/AD5542A/AD5512AA
Bipolar Output Operation ......................................................... 14 Output Amplifier Selection ....................................................... 14 Force Sense Amplifier Selection ............................................... 14 Reference and Ground ............................................................... 14 Power-On Reset........................................................................... 15 Power Supply and Reference Bypassing ................................... 15 Microprocessor Interfacing ........................................................... 16 AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface........ 16 AD5541/AD5542 to 68HC11/68L11 Interface ....................... 16 AD5541/AD5542 to MICROWIRE Interface ......................... 16 AD5541/AD5542 to 80C51/80L51 Interface........................... 16 Applications Information ............................................................... 17 Optocoupler Interface ................................................................ 17 Decoding Multiple AD5541/AD5542s..................................... 17 Outline Dimensions ........................................................................ 18 Ordering Guide ........................................................................... 21
REVISION HISTORY
Rev. PrA | Page 3 of 24
AD5541A/AD5542A/AD5512A SPECIFICATIONS
Preliminary Technical Data
VDD = 2.7 V to 5.5V, VREF = 2.5 V, AGND = DGND = 0 V. -40C < TA < +105C, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE AD5541A/AD5542A Resolution Relative Accuracy (INL) Min Typ Max Unit Test Condition
16 0.5 0.5 0.5 0.5 1.0 2.0 4.0 1.0 1.5
Differential Nonlinearity (DNL) AD5512A Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient AD5542A/AD5512A Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance1 LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VINH Input High Voltage, VINH Input Capacitance2 Hysteresis Voltage2 REFERENCE Reference -3 dB Bandwidth Reference Feedthrough THD Signal-to-Noise Ratio Reference Input Capacitance
Bits LSB LSB LSB LSB LSB Bits LSB LSB LSB LSB ppm/C LSB LSB ppm/C / % LSB LSB ppm/C V V s V/s nV-sec nV-sec k LSB V k k A V V V pF V MHz mV p-p dB dB pF pF
L, C grades B, J grades A grade Guaranteed monotonic J grade
12 1.0 1.0 5 7 1 2
-1.5 0.1 0.3 0.05 1.000 0.0015 1 0.2 0 -VREF 1 25 0.5 0.2 6.25
TA = 25C
TA = 25C
TBD 5 7
RFB/RINV, typically RFB = RINV = 28 k Ratio error TA = 25C
VREF - 1 LSB +VREF - 1 LSB
1.0 2.0 9 7.5 VDD
Unipolar operation AD5542 bipolar operation To 1/2 LSB of FS, CL = 10 pF CL = 10 pF, measured from 0% to 63% 1 LSB change around the major carry All 1s loaded to DAC, VREF = 2.5 V Tolerance typically 20% VDD 10%
Unipolar operation AD5542, bipolar operation
1 0.8 2.0 1.8 10 0.15 1.3 1 TBD 92 75 120
Rev. PrA | Page 4 of 24
VDD = 2.7 V to 5.5 V VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V
All 1s loaded All 0s loaded, VREF = 1 V p-p at 100 kHz
Code 0x0000 Code 0xFFFF
Preliminary Technical Data
Parameter POWER REQUIREMENTS VDD IDD VLOGIC ILOGIC Power Dissipation
1 2
AD5541A/AD5542A/AD5512AA
Typ Max 5.5 TBD 5.5 TBD TBD Unit V A V A mW Test Condition
Min 2.7
200 1.8 200 1.5
Reference input resistance is code-dependent, minimum at 0x8555. Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VLOGIC = 1.8 V to 5.5 V V, VDD = 5V, VREF = 2.5 V, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V; -40C < TA < +105C,
unless otherwise noted.
Table 2.
Parameter1, 2 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t9 t10 t11 t12 t13
1 2
Limit 50 20 10 10 5 7 15 10 7 5 5 15 15 15 15
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK cycle frequency SCLK cycle time SCLK high time SCLK low time CS low to SCLK high setup CS high to SCLK high setup SCLK high to CS low hold time SCLK high to CS high hold time Data setup time Data hold time (VINH = 90% of VDD, VINL = 10% of VDD) Data hold time (VINH = 3V, VINL = 0 V) LDAC pulsewidth CS high to LDAC low setup CS high time between active periods CLR pulsewidth
Guaranteed by design and characterization. Not production tested All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
Figure 5. Timing Diagram
Rev. PrA | Page 5 of 24
AD5541A/AD5542A/AD5512A ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to AGND Digital Input Voltage to DGND VOUT to AGND AGND, AGNDF, AGNDS to DGND Input Current to Any Pin Except Supplies Operating Temperature Range Industrial (A, B, C Versions) Commercial (J, L Versions) Storage Temperature Range Maximum Junction Temperature (TJ max) Package Power Dissipation Thermal Impedance, JA SOIC (R-8) SOIC (R-14) Lead Temperature, Soldering Peak Temperature1
1
Preliminary Technical Data
Rating -0.3 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +0.3 V 10 mA -40C to +85C 0C to 70C -65C to +150C 150C (TJ max - TA)/JA 149.5C/W 104.5C/W 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
As per JEDEC Standard 20.
Rev. PrA | Page 6 of 24
Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF CS SCLK DIN 1 2 3 4 NC = NO CO NNECT 8 GND
VDD VOUT AGND REF
00000-000
AD5541A/AD5542A/AD5512AA
1 2 3 4 5 NC = NO CO NNECT
10 VLOGIC
AD5541A-1
TO P V IE W (N o t to S cale)
7 VDD 6 VOUT 5 CLR
AD5541A
TO P V IE W (N o t to S cale)
9 8 7 6
DGND LDAC DIN
00000-000
CS
SCLK
Figure 6. AD5541A-1 8-Lead LFCSP Pin Configuration
Figure 8. AD5541A 10-Lead LFCSP Pin Configuration
VDD VOUT
1 2 3 4 5
10
VLOGIC DGND LDAC DIN SCLK
VO UT AGND REF CS
1 2 3 4
8
AD5541A
TO P V IE W (N o t to S cale)
V DD DGND D IN SCLK
07557-004
AGND REF CS
AD5541A
TOP VIEW (Not to Scale)
9 8 7 6
7 6 5
NC = NO CONNECT
Figure 7. AD5541A 8-Lead SOIC Pin Configuration
Figure 9. AD5541A 10-Lead MSOP Pin Configuration
Table 4. AD5541A Pin Function Descriptions
8-Lead LFCSP 6 1 2 3 4 Pin No. 8-Lead 10-Lead SOIC LFCSP 1 2 2 3 3 4 4 5 6 7 8 5 6 7 9 1 10-Lead MSOP 2 3 4 5 6 7 9 1
Mnemonic VOUT AGND REF CS SCLK DIN DGND VDD CLR
7 5
10 8
10 8
VLOGIC LDAC
Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V 10%. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are cleared to the model selectable midscale or zeroscale . Logic Power Supply. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register.
Rev. PrA | Page 7 of 24
AD5541A/AD5542A/AD5512A
Preliminary Technical Data
RFB VOUT
1 2 16 15
VDD VLOGIC INV DGND LDAC CLR DIN SCLK
AGNDF 3 AGNDS 4 REFS REFF NC CS
5 6 7 8
A D 5542A
TO P V IE W (N o t to S cale)
14 13 12 11 10 9
NC = NO CO NNECT
Figure 10. AD5542A-1 10-Lead LFCSP Pin Configuration
Figure 12. AD5542A 16-Lead TSSOP Pin Configuration
14 VLOGIC
16 RFB
15 VDD
RFB V O UT AG NDF AG NDS REFS REFF CS
1 2 3 4 5 6 7
14 V D D 13 IN V
VOUT
1
13 INV
12 DGND
AD5542A
12 D G N D
AGNDF 2 AGNDS 3 REFS 4
5
AD5542A AD5512A
TO P V IE W
11 LDAC 10 CLR 9
SCLK 8
TO P V IE W 11 L D A C (N o t to S cale) 10 D IN
9 8
DIN
00000-000
NC
07557-005
SCLK
Figure 11. AD5542 14-Lead SOIC Pin Configuration
Figure 13. AD5542A 16-Lead LFCSP Pin Configuration
Table 5. AD5542A/AD5512A Pin Function Descriptions
10-Lead LFCSP 8 6 Pin No. 14-Lead 16-Lead SOIC TSSOP 1 1 2 3 4 5 6 2 3 7 8 2 3 4 5 6 8 9 16-Lead LFCSP 16 1 2 3 4 5 6 8
Mnemonic RFB VOUT AGNDF AGNDS REFS REFF CS SCLK
5 4 10 11 12 13 14
11 10 12 13 14 16 15
10 9 11 12 13 15 14
CLR DIN LDAC DGND INV VDD VLOGIC
7 9
Description Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry (Force). Ground Reference Point for Analog Circuitry (Sense). Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are cleared to the model selectable midscale or zeroscale . Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. Digital Ground. Ground reference for digital circuitry. Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. Analog Supply Voltage, 5 V 10%. Logic Power Supply.
Rev. PrA | Page 8 of 24
NC
CS
NC = NO CO NNECT
REFF
NC = NO CO NNECT (N o t to S cale)
6
7
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD5541A/AD5542A/AD5512AA
Figure 14. Integral Nonlinearity vs. Code
Figure 17. Differential Nonlinearity vs. Code
Figure 15. Integral Nonlinearity vs. Temperature
Figure 18. Differential Nonlinearity vs. Temperature
Figure 16. Linearity Error vs. Supply Voltage
Figure 19. Linearity Error vs. Reference Voltage
Rev. PrA | Page 9 of 24
AD5541A/AD5542A/AD5512A
Preliminary Technical Data
Figure 20. Gain Error vs. Temperature
Figure 23. Zero-Code Error vs. Temperature
Figure 21. Supply Current vs. Temperature
Figure 24. Supply Current vs. Reference Voltage or Supply Voltage
Figure 22. Supply Current vs. Digital Input Voltage
Figure 25. Reference Current vs. Code
Rev. PrA | Page 10 of 24
Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Figure 26. Digital Feedthrough
Figure 28. Large Signal Settling Time
Figure 27. Digital-to-Analog Glitch Impulse
Figure 29. Small Signal Settling Time
Rev. PrA | Page 11 of 24
AD5541A/AD5542A/AD5512A TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 14. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. A typical DNL vs. code plot is shown in Figure 17. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C. Zero Code Error Zero code error is a measure of the output error when zero code is loaded to the DAC register. Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/C.
Preliminary Technical Data
Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure 27. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the CLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical digital feedthrough plot is shown in Figure 26. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by 10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
Rev. PrA | Page 12 of 24
Preliminary Technical Data THEORY OF OPERATION
The AD5541A/AD5542A/AD5512A are single, 16-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5 V and consume typically 300 A with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function. In unipolar mode, the output is reset to 0 V; in bipolar mode, the AD5542 output is set to -VREF. Kelvin sense connections for the reference and analog ground are included on the AD5542.
AD5541A/AD5542A/AD5512AA
SERIAL INTERFACE
The AD5541/AD5542 are controlled by a versatile 3- or 4-wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 5. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 16-bit words. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can be loaded to the part only while CS is low. The AD5542 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC can be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS loads the data to the DAC.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 30. The DAC architecture of the AD5541/AD5542 is segmented. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data-word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R R VOUT 2R E1 2R . . . . . E2 . . . . . 2R E15
UNIPOLAR OUTPUT OPERATION
These DACs are capable of driving unbuffered loads of 60 k. Unbuffered operation results in low supply current, typically 300 A, and a low offset error. The AD5541 provides a unipolar output swing ranging from 0 V to VREF. The AD5542 can be configured to output both unipolar and bipolar voltages. Figure 31 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 6.
5V 2.5V 10F
2R
2R S0
2R . . . . . S1 . . . . .
2R S11
VREF
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS
Figure 30. DAC Architecture
07557-022
With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation:
0.1F
0.1F
SERIAL INTERFACE
CS DIN
VDD REF(REFF*) REFS*
+
VOUT =
VREF x D 2N
AD5541/AD5542
DGND AGND
AD820/ OP196
OUT EXTERNAL OP AMP
SCLK LDAC*
UNIPOLAR OUTPUT
where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following:
*AD5542 ONLY.
Figure 31. Unipolar Output
Table 6. Unipolar Code Table
DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 Analog Output VREF x (65,535/65,536) VREF x (32,768/65,536) = 1/2 VREF VREF x (1/65,536) 0V
VOUT =
2. 5 x D 65,536
This gives a VOUT of 1.25 V with midscale loaded, and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/65,536.
Rev. PrA | Page 13 of 24
07557-023
AD5541A/AD5542A/AD5512A
Assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation:
Preliminary Technical Data
Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation:
VOUT -UNI =
D x (VREF + VGE ) + V ZSE + INL 216
VOUT -BIP =
[(V
OUT - UNI
+ VOS 2 + RD ) - VREF (1 + RD ) 1 + (2 + RD ) A
)(
]
where: VOUT-UNI is unipolar mode worst-case output. D is code loaded to DAC. VREF is reference voltage applied to the part. VGE is gain error in volts. VZSE is zero scale error in volts. INL is integral nonlinearity in volts.
where: VOUT-BIP is the bipolar mode worst-case output VOUT-UNI is the unipolar mode worst-case output. VOS is the external op amp input offset voltage. RD is the RFB and RINV resistor matching error. A is the op amp open-loop gain.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5542 can be configured to provide a bipolar voltage output. A typical circuit of such operation is shown in Figure 32. The matched bipolar offset resistors, RFB and RINV, are connected to an external op amp to achieve this bipolar output swing, typically RFB = RINV = 28 k. Table 7 shows the transfer function for this output operating mode. Also provided on the AD5542 are a set of Kelvin connections to the analog ground inputs.
+5V +2.5V 10F 0.1F 0.1F
+
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and supplied from a dual power supply. This provides the VREF output. In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case, AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have a very low-offset voltage (the DAC LSB is 38 V with a 2.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 k), adds to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier.
SERIAL INTERFACE
RFB VDD CS DIN SCLK LDAC DGND AGNDF AGNDS RINV REFF REFS RFB INV
+5V
OUT
AD5541/AD5542
UNIPOLAR OUTPUT
07557-024
-5V EXTERNAL OP AMP
Figure 32. Bipolar Output (AD5542 Only)
Table 7. Bipolar Code Table
DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 Analog Output +VREF x (32,767/32,768) +VREF x (1/32,768) 0V -VREF x (1/32,768) -VREF x (32,768/32,768) = -VREF
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred because the amplifiers need to be able to handle dynamic currents of up to 20 mA.
REFERENCE AND GROUND
Because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The AD5541/ AD5542 operate with a voltage reference ranging from 2 V to VDD. References below 2 V result in reduced accuracy. The fullscale output voltage of the DAC is determined by the reference. Table 6 and Table 7 outline the analog output voltage or particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5542. If the application doesn't require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die.
Rev. PrA | Page 14 of 24
Preliminary Technical Data
POWER-ON RESET
The AD5541/AD5542 have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541/ AD5542 need to be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs.
AD5541A/AD5542A/AD5512AA
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor.
Rev. PrA | Page 15 of 24
AD5541A/AD5542A/AD5512A MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5541/AD5542 is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD5541/AD5542 require a 16-bit data-word with data valid on the rising edge of SCLK. The DAC update can be done automatically when all the data is clocked in or it can be done under control of the LDAC (AD5542 only).
Preliminary Technical Data
AD5541/AD5542 TO MICROWIRE INTERFACE
Figure 35 shows an interface between the AD5541/AD5542 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5541/ AD5542 on the rising edge of the serial clock. No glue logic is required because the DAC clocks data into the input shift register on the rising edge.
CS CS DIN SCLK
Figure 33 shows a serial interface between the AD5541/AD5542 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out on each rising edge of the serial clock, an inverter is required between the DSP and the DAC, because the AD5541/AD5542 clock data in on the falling edge of the SCLK.
FO LDAC** CS DIN SCLK
07557-025
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5541/AD5542 to MICROWIRE Interface
AD5541/AD5542 TO 80C51/80L51 INTERFACE
A serial interface between the AD5541/AD5542 and the 80C51/ 80L51 microcontroller is shown in Figure 36. TxD of the microcontroller drives the SCLK of the AD5541/AD5542, and RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port that is used to drive CS. The 80C51/80L51 provide the LSB first, whereas the AD5541/ AD5542 expects the MSB of the 16-bit word first. Care should be taken to ensure the transmit routine takes this into account. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmit data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 16-bit word, P3.3 must be left low after the first eight bits are transferred, and brought high after the second byte is transferred. LDAC on the AD5542 can also be controlled by the 80C51/ 80L51 serial port output by using another bit programmable pin, P3.4.
P3.4 LDAC** CS DIN SCLK
07557-028
ADSP-2101/ TFS ADSP-2103* DT
SCLK
AD5541/ AD5542*
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY.
Figure 33. AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface
AD5541/AD5542 TO 68HC11/68L11 INTERFACE
Figure 34 shows a serial interface between the AD5541/AD5542 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ 68L11 drives the SCLK of the DAC, and the MOSI output drives the serial data line serial DIN. The CS signal is driven from one of the port lines. The 68HC11/68L11 is configured for master mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK.
PC6 LDAC** CS DIN SCLK
07557-026
80C51/ 80L51*
P3.3 RxD TxD
AD5541/ AD5542*
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY.
68HC11/ 68L11*
PC7 MOSI SCK
AD5541/ AD5542*
Figure 36. AD5541/AD5542 to 80C51/80L51 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY.
Figure 34. AD5541/AD5542 to 68HC11/68L11 Interface
Rev. PrA | Page 16 of 24
07557-027
AD5541/AD5542 TO ADSP-2101/ADSP-2103 INTERFACE
MICROWIRE*
SO SCLK
AD5541/ AD5542*
Preliminary Technical Data APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5541A/AD5542A/AD5512A are Schmitt-triggered so that they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary to isolate the DAC from the controller via optocouplers. Figure 37 illustrates such an interface.
5V REGULATOR 10F
AD5541A/AD5542A/AD5512AA
DECODING MULTIPLE AD5541/AD5542s
The CS pin of the AD5541/AD5542 can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device receives the CS signal at any one time. The DAC addressed is determined by the decoder. There is some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 38 shows a typical circuit.
SCLK DIN VDD
POWER
0.1F
AD5541/AD5542
CS DIN SCLK VOUT
VDD 10k SCLK SCLK VDD
ENABLE CODED ADDRESS
EN DECODER
AD5541/AD5542
CS DIN SCLK DGND VOUT
VDD 10k CS
AD5541/AD5542
CS
VOUT
AD5541/AD5542
CS DIN SCLK VOUT
VDD 10k DIN DIN GND
07557-029
AD5541/AD5542
CS DIN SCLK VOUT
07557-030
Figure 37. AD5541/AD5542 in an Optocoupler Interface
Figure 38. Addressing Multiple AD5541/AD5542s
Rev. PrA | Page 17 of 24
OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters.
3.00 BSC SQ
0.30 0.23 0.18
6 10 EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.19)
Figure 40. 10-Lead Lead Frame Chip Scale Package [LFCSP] (CP-10-9) Dimensions shown in millimeters.
Rev. PrA | Page 18 of 24
101207-B
0.20 REF
3.00 BSC SQ
0.35 0.30 0.25
5 8 EXPOSED PAD (BOTTOM VIEW)
0.65 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
4
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.2)
Figure 41. 8-Lead Lead Frame Chip Scale Package [LFCSP] (CP-8-3) Dimensions shown in millimeters.
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 42. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters.
Rev. PrA | Page 19 of 24
041608-B
0.20 REF
PIN 1 INDICATOR
3.10 3.00 SQ 2.90 0.50 BSC
0.30 0.23 0.18
13 12 EXPOSED PAD 16 1
PIN 1 INDICATOR
1.75 1.60 SQ 1.55
4
9
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.50 0.40 0.30
8
5
BOTTOM VIEW
0.25 MIN
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
020509-B
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP] (CP-16-22) Dimensions shown in millimeters.
Rev. PrA | Page 20 of 24
ORDERING GUIDE
Model AD5541ABRMZ AD5541AARMZ AD5541ABCPZ AD5541AACPZ AD5541ABCPZ-1 AD5542ABRUZ AD5542AARUZ AD5542ASRUZ AD5542ABCPZ AD5542AACPZ AD5442ABCPZ-1 AD5512AACPZ INL 1 LSB 2 LSB 1 LSB 2 LSB 1 LSB 1 LSB 2 LSB 1 LSB 1 LSB 2 LSB 1 LSB 1 LSB DNL 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB Clear to Code Midscale Midscale Midscale Midscale Zero-scale Midscale Midscale Midscale Midscale Midscale Midscale Midscale Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -55C to +125C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead LFCSP 8-Lead LFCSP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP 16-Lead LFCSP 10-Lead LFCSP 16-Lead LFCSP Package Option RM-10 RM-10 CP-10-9 CP-10-9 CP_8-3 RU-16 RU-16 RU-16 CP-16-22 CP-16-22 CP-10-9 CP-16-22
Rev. PrA | Page 21 of 24
AD5541A/AD5542A/AD5512A NOTES
Preliminary Technical Data
Rev. PrA | Page 22 of 24
Preliminary Technical Data NOTES
AD5541A/AD5542A/AD5512A
Rev. PrA | Page 23 of 24
AD5541A/AD5542A/AD5512A NOTES
Preliminary Technical Data
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08516-0-12/09(PrA)
Rev. PrA | Page 24 of 24

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